The present invention relates generally to the field of integrated circuit testing and, more particularly, to a method and an apparatus for performing circuit edits in an integrated circuit for the purpose of verifying design engineering change orders.
Once a newly designed integrated circuit has be en formed on a semiconductor substrate, the integrated circuit must be thoroughly tested to ensure that the circuit performs as designed. Portions of the integrated circuit that do not function properly are identified so that they can be fixed by correcting the design of the integrated circuit. This process of testing an integrated circuit to identify problems with its design is known as debugging. After debugging the integrated circuit and correcting any problems with its design, the final fully functional integrated circuit designs are used to mass produce the integrated circuits in a manufacturing environment for consumer use.
During the debugging process, it is sometimes necessary to add, delete or reroute signal line connections within the integrated circuit. For instance, assume that FIG. 1A shows an integrated circuit 101 that requires edits to be made. In this example, circuit block A 103 is coupled to circuit block B 107 through inverter 105. If it is determined during the debug process that the signal from circuit block A 103 should not be inverted when received by circuit block B 107, integrated circuit 101 may be edited in a way such that inverter 105 is effectively removed from integrated circuit 101 and that circuit block A 103 is directly connected to circuit block B 107.
Using prior art techniques, integrated circuit 101 may be edited as follows. Inverter 105 may be disconnected from circuit block A 103 and circuit block B 107 by physically cutting the signal line through the front side of the integrated circuit die as shown in FIG. 1A with cut 111. After cut 111 is made, circuit block A 103 is no longer connected to circuit block B 107 through inverter 105. In order to reconnect circuit block A 103 and circuit block B 107, dielectric is removed from the front side of the integrated circuit die at locations 113 and 115 to expose the buried metal of the signal line connected to circuit block A 103 and circuit block B 107. After the dielectric is removed from the signal line at locations 113 and 115, a new metal line 117 is deposited over the dielectric on the front side of the integrated circuit die and over the exposed pieces of metal at locations 113 and 115 to directly connect circuit block A 103 to circuit block B 107.
FIG. 1B is an illustration of a cross-section of an integrated circuit package 121 including an integrated circuit die 125 on which circuit edits have been performed. As shown in FIG. 1B, integrated circuit package 121 includes wire bonds 123 disposed along the periphery of integrated circuit die 125 to electrically connect integrated circuit connections through metal interconnects 128 and 129 to pins 127 of the package substrate 131. Metal interconnects 128 and 129 are disposed in a dielectric isolation layer 141 of integrated circuit die 125, and are coupled to diffusion regions 135, 137 and 139.
It is noted that before the circuit edits shown in FIG. 1B were performed in integrated circuit die 125, diffusion 137 was coupled to diffusion 139 through metal interconnect 129. In addition, diffusion 135 was not coupled to diffusion 137. FIG. 1B shows circuit edits that have been performed to disconnect diffusion 137 from diffusion 139 and connect diffusion 135 to diffusion 137. As shown in FIG. 1B, diffusion 137 has been disconnected from diffusion 139 with metal interconnect 129 being physically cut by milling a hole 132 through the dielectric isolation layer 141 from the front side 145 of integrated circuit die 125. As shown in FIG. 1B, diffusion 137 has been disconnected from diffusion 139 as a result of hole 132. As shown in FIG. 1B, circuit edits have also been performed to connect diffusion 135 to diffusion 137. A hole 133 has been milled through dielectric isolation layer 141 from the front side 145 of integrated circuit die 125 to expose a portion of metal interconnect 128. Similarly, a hole 134 has been milled through dielectric isolation layer 141 from the front side 145 of integrated circuit die 125 to expose a portion of metal interconnect layer 129. A conductor 130 has then been deposited over the dielectric isolation layer 141 and holes 133 and 134 to connect metal interconnect 128 to metal interconnect 129, thereby connecting diffusion 135 to diffusion 137.
As mentioned above, it is noted that integrated circuit package 121 of FIG. 1B is of a wire bond design. There are several disadvantages associated with the wire bond design of integrated circuit package 121. One problem stems from the fact that as the density and complexity of integrated circuit die 125 increases, so must the number of wire bonds 123 required to control the functions integrated circuit die 125. However, there are only a finite number of wire bonds 123 that can fit along the periphery of integrated circuit die 125. One way to fit more wire bonds 125 along the periphery of integrated circuit die 125 is to increase the overall size of integrated circuit die 125, thereby increasing its peripheral area. Unfortunately, an increase in the overall size of integrated circuit die 125 also significantly increases the integrated circuit manufacturing costs.
Another disadvantage with integrated circuit package 121 of FIG. 1B is that the active circuitry within integrated circuit die 125 must be routed through metal interconnects 128 and 129 to the peripheral region of integrated circuit die 125 in order to electrically couple the active circuitry to wire bonds 123. By routing metal interconnect lines 128 and 129 over a relatively long distance across the integrated circuit die 125, the increased resistive, capacitive and inductive effects of these lengthy interconnect lines results in an overall speed reduction of the integrated circuit device. In addition, the inductance of wire bonds 123 may also severely limit high frequency operation of integrated circuit devices in integrated circuit package 121.
With continuing efforts in the integrated circuit industry to increase integrated circuit speeds as well device densities, there is a trend towards using flip-chip technology when packaging complex high speed integrated circuits. Flip-chip technology is also known as control collapse chip connection (C4) packaging. In flip-chip packaging technology, the integrated circuit die is flipped upside-down. This is opposite to how integrated circuits are packaged today using wire bond technology, as illustrated in FIG. 1B. By flipping the integrated circuit die upside-down, ball bonds may be used to provide direct electrical connections from the bond pads directly to the pins of a flip-chip package.
To illustrate, FIG. 1C shows a flip-chip package 151 with an integrated circuit die 155 flipped upside-down relative to wire bonded integrated circuit die 125 of FIG. 1B. In comparison with wire bonds 123 of FIG. 1B, ball bonds 153 of flip-chip package 151 provide more direct connections between the circuitry in integrated circuit die 155 and the pins 157 of package substrate 161 through metal interconnects 169 and 171. As a result, the inductance problems that plague the typical wire bond integrated circuit packaging technologies are reduced. Unlike wire bond technology, which only allows bonding along the periphery of the integrated circuit die 155, flip-chip technology allows connections to be placed anywhere on the integrated circuit die surface. This results in reduced inductance power distribution to the integrated circuit which is another major advantage of flip-chip technology.
One consequence of integrated circuit die 155 being flipped upside-down in flip-chip package 151 is that access to the internal nodes of integrated circuit die 155 for circuit edit purposes has become a considerable challenge. As illustrated in FIG. 1B, prior art circuit editing techniques used with wire bond technology are based on performing the circuit edits on metal interconnects 128 and 129 through the front side 145 of the integrated circuit die 125. However, with flip-chip packaging technology, this front side methodology is not feasible since the integrated circuit die is flipped upside-down. For example, as illustrated in FIG. 1C, circuit edit access to metal interconnects 169 and 171 through the front side 173 of integrated circuit die 155 is obstructed by package substrate 161. In addition, diffusion regions 163, 165 and 167 obstruct circuit edit access to metal interconnects 169 and 171 from the backside 175 of the semiconductor substrate of integrated circuit die 155.
Thus, what is desired is a method and apparatus enabling circuit edits to be performed in a flip-chip packaged integrated circuit though the backside of an integrated circuit die.
A method for making a circuit edit interconnect structure on an integrated circuit die is disclosed. In one embodiment, the method for performing a circuit edit in an integrated circuit die includes the steps of exposing from a backside of the integrated circuit die first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die, vapor depositing a polyimide layer over the semiconductor substrate of the integrated circuit die between the first and second circuit edit connection targets, and depositing a conductor over the polyimide layer between the first and second circuit edit connection targets to couple together the first and second circuit edit connection targets.